WASHINGTON, Global semiconductor foundry capacity is structurally bifurcated: leading-edge nodes running below 7nm face record AI demand that is absorbing available wafer starts and advanced packaging slots, while legacy nodes at 28nm and above: the substrate for most IoT chips, automotive MCUs, and analog ICs, are recovering from a 2020–2022 shortage that exposed how fragile high-volume, low-margin process tiers had become. Both tiers face distinct constraints, and both matter to the electronics supply chain.
The 2020–2022 Shortage: What Broke and Why
The 2020–2022 global chip shortage was predominantly a legacy-node crisis. Production disruptions from COVID-19 coincided with a surge in PC, consumer electronics, and automotive demand that overwhelmed fabs operating at 28nm, 40nm, and 65nm nodes. These process tiers manufacture the microcontrollers, power management ICs, display drivers, and wireless connectivity chips embedded in virtually every electronic device. They are also the tiers where capital investment had been lightest, foundries had little economic incentive to expand capacity for mature nodes with thin margins when advanced-node fabs captured headlines and premium pricing.
Lead times for automotive-grade MCUs stretched beyond 52 weeks at the peak of the shortage. Silicon Labs publicly warned in its Q3 2021 earnings disclosures that foundry capacity shortfalls were directly restricting IoT chip shipments, a concrete signal that consumer and industrial IoT production had entered allocation-driven constraint. TSMC, Samsung, and UMC collectively controlled the majority of mature-node wafer starts, and none had sufficient 28nm headroom to absorb the demand spike. UMC’s revenue rose 14 percent year-on-year in 2021, driven almost entirely by legacy-node pricing power as buyers competed for allocation slots.
The structural vulnerability was straightforward: a single advanced-node fab costs 5–20 billion to construct and takes three to four years to reach full production ramp. Mature-node fabs are cheaper: approximately –7 billion for a 28nm greenfield facility, but the return-on-investment calculus had discouraged expansion for over a decade. When demand spiked across multiple end markets simultaneously, the buffer capacity was not there.
GLOBALFOUNDRIES, which exited the leading-edge race at 7nm in 2018, emerged as a significant capacity provider for legacy nodes. Its Malta, New York and Dresden facilities, both operating at 12nm to 180nm, became critical supply sources for automotive and industrial customers who could not source product from TSMC or Samsung during the shortage period.
Legacy Nodes vs. Leading Edge: Different Crises
The 28nm node and its sub-nodes (22nm, 40nm, 65nm) account for approximately 70 percent of global wafer demand by unit volume. The chips produced at these nodes: IoT sensors, Wi-Fi and Bluetooth SoCs, automotive radar ICs, analog mixed-signal devices, are overwhelmingly manufactured at 28nm and above. The Semiconductor Industry Association estimates that legacy-node fabs will continue to carry the bulk of global unit production through at least 2030, regardless of the revenue and margin concentration in advanced nodes.
Recovery in mature-node capacity utilization has been uneven. Average utilization across 28nm and above rose 5–10 percent in the second half of 2024 compared to the first, but remained below 80 percent at most facilities through late 2024. New capacity additions from Chinese foundries, SMIC, Hua Hong Semiconductor, and Nexchip, have added pressure on mature-node pricing, with average selling prices for 28nm wafers declining as Chinese fabs aggressively competed for non-restricted customers. TSMC’s Dresden facility, expected to begin production in 2027, targets automotive customers with 12nm, 16nm, 22nm, and 28nm process technologies: an explicitly legacy-node investment driven by European automotive demand rather than AI.
The leading-edge tier tells a different story. TSMC’s 3nm and 5nm nodes are running at near-full utilization, with AI accelerators and high-performance computing (HPC) chips consuming the majority of available wafer starts. Apple’s A-series SoCs (5nm/N3B), Nvidia’s H100 and B200 GPU dies (4nm/N4P and 4nm/N4P), and AMD’s EPYC server CPUs (5nm/N5) compete for the same fabrication slots. TSMC controls roughly 90 percent of global advanced-node foundry revenue, with Samsung’s 3GAE gate-all-around process holding the remainder at sub-5nm. Intel’s 18A node, its first competitive leading-edge process in several years, is scheduled to enter risk production in 2025 at the Ronler Acres facility in Hillsboro, Oregon.
AI Demand and the New Capacity Squeeze
Nvidia’s H100 GPU, built on TSMC’s N4 process, and the successor B200 built on N4P, have created a capacity concentration problem with no historical precedent. More than 70 percent of TSMC’s next-generation CoWoS-L advanced packaging capacity for 2025 was pre-committed by a single customer. TSMC’s entire CoWoS lineup, CoWoS-L and CoWoS-S: is fully booked through 2025 and into 2026, according to TrendForce. The CoWoS constraint is not a silicon shortage; it is a packaging throughput bottleneck. Each H100/H200 or B200 module requires a CoWoS interposer that integrates the GPU die with multiple stacks of High Bandwidth Memory (HBM3 or HBM3e). TSMC’s CoWoS capacity stood at approximately 75,000–80,000 wafer-equivalents per month in early 2025; the company targets expansion to 120,000–130,000 per month by end of 2026.
The downstream effect on non-AI silicon is real. AMD’s consumer Ryzen processors and Apple’s Mac SoCs compete for N4/N5 wafer starts against data center AI accelerators that generate two to three times the wafer revenue per unit. Hyperscale customers, Google, Amazon, Microsoft, have signed multi-year capacity reservation agreements with TSMC, locking in wafer-start allocations that reduce the spot-market supply available to mid-tier fabless customers. IoT chip designers sourcing advanced connectivity silicon at 7nm or 5nm face extended lead times not because their volumes are large, but because the priority queue favors higher-margin AI workloads.
SEMI reported in early 2025 that advanced foundry capacity, broadly defined as sub-10nm: would maintain a compound annual growth rate of 14 percent through 2028, with total installed capacity surpassing one million wafers per month for the first time in 2026. Total global 300mm fab capacity reached approximately 9.0 million wafers per month by early 2026 across all node sizes. The growth is real but concentrated: the new capacity is primarily AI-serving leading-edge production, not the legacy-node expansion that IoT supply chains require.
CHIPS Act Funding: What Gets Built
The CHIPS and Science Act (Pub.L. 117-167), enacted August 9, 2022, appropriated 2.7 billion for U.S. semiconductor manufacturing, research, and workforce development. Of that total, 9 billion was designated for manufacturing incentives administered by the Department of Commerce. As of November 2025, over 6 billion in awards had been finalized.
The three largest recipients reflect the leading-edge concentration of the program. TSMC received a .6 billion direct funding award for its Arizona Fab 21 complex in Phoenix. Phase 1, producing on TSMC’s 4nm N4 process, entered volume production in the first half of 2025, with yield rates exceeding 92 percent. Phase 2 construction is complete, with equipment installation underway for 3nm and 2nm production targeted for 2027. Intel received a modified award of .86 billion for its Ohio One campus in New Albany and its Arizona facilities, with production ramp on Intel 18A process targeted for 2025–2026. Samsung’s Taylor, Texas facility received a reduced award of .7 billion after due diligence; mass production of leading-edge logic has been pushed to late 2026.
GLOBALFOUNDRIES secured a .5 billion award for legacy-node expansion at its Malta, New York fab, the most explicit CHIPS Act investment in non-leading-edge capacity. The Malta facility produces at 12nm to 180nm for defense, automotive, and IoT customers, and GLOBALFOUNDRIES has positioned it as the primary onshore supply source for legacy-node U.S. government procurement under the National Defense Authorization Act requirements for trusted foundry sourcing. Micron’s DRAM investment in Boise, Idaho received a .1 billion commitment. The NIST Manufacturing USA institutes funded under the act’s research provisions include programs specifically targeting advanced packaging, a direct response to the CoWoS bottleneck identified as a national security supply chain risk.
The CHIPS Act investments are not a short-term supply fix. Fab construction takes three to five years; full production ramp adds another one to two years. TSMC Arizona Phase 1, the fastest CHIPS Act project to production: took approximately three years from groundbreaking to volume yield. The Ohio and Texas facilities will not materially contribute to domestic supply until 2027 at the earliest. For IoT and automotive supply chain planners, the domestic capacity being built now provides risk mitigation for the 2027–2030 horizon, not the current procurement cycle.
What’s Next: Capacity Outlook 2025–2027
SEMI projects total installed semiconductor fab capacity to grow 4.7 percent in 2026 and 5.0 percent in 2027. Eighteen new fabs were reported under construction globally as of early 2025. The growth skews heavily toward advanced nodes and toward geographic diversification, the CHIPS Act, the European Chips Act (€43 billion), Japan’s Rapidus initiative (targeting 2nm at Chitose, Hokkaido), and India’s Tata Electronics foundry project in Dholera collectively represent the largest geographic redistribution of fab capacity since the 1990s.
For legacy-node IoT supply chains, the picture is mixed. Chinese foundry expansion at 28nm, SMIC’s new facilities in Beijing and Shanghai, Hua Hong’s Wuxi fab, has added wafer-start capacity but is partially offset by U.S. export controls that restrict the equipment Chinese fabs can purchase (see CHIPS Act: Semiconductor Investment and Export Controls). Chinese fabs cannot acquire ASML EUV systems and face restrictions on advanced DUV immersion tools, capping their process node at approximately N+2 (roughly equivalent to 7nm class using multi-patterning). For 28nm and above, however, Chinese foundries are building genuine capacity that will suppress global mature-node pricing and reduce the shortage risk that characterized 2020–2022.
Lead times for 28nm IoT chips have normalized from the 52-week peaks of 2021 to approximately 14–20 weeks as of early 2025, a level consistent with pre-shortage averages. Power management and analog ICs: the last legacy-node categories to recover — moved off allocation through 2024. The shortage cycle appears closed for now. The structural question is whether the capacity added during the shortage response — including GLOBALFOUNDRIES Malta and the new Chinese fabs — creates excess mature-node supply that suppresses investment incentives for the next decade, leaving the same vulnerability in place for the next demand spike.
At the leading edge, AI demand shows no sign of abating. SEMI’s equipment spending forecast projects foundry and logic equipment investment reaching 5.2 billion in 2026, up from 6.6 billion in 2025. TSMC’s capital expenditure guidance for 2025 was 8–42 billion, the majority directed at N3 and N2 capacity expansion. The CoWoS advanced packaging constraint will ease as TSMC and OSAT partners including ASE — which projects its own CoWoS-equivalent capacity rising to 20,000–25,000 wafer-equivalents per month by end of 2025 — add throughput. But the demand curve for AI silicon is tracking faster than capacity additions, and any non-AI chip competing for leading-edge wafer starts faces a structural disadvantage that will persist into the late 2020s.
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